Field of the Invention
The invention relates to a memory cell configuration for the nonvolatile storage of data.
For the nonvolatile storage of data, memory cell configurations are often used in which the memory cell in each case contains a conventional MOS transistor which has a floating gate in addition to a control gate. Charges corresponding to information to be stored are stored on the floating gate (see the reference by S. M Sze, titled xe2x80x9cSemiconductor Devicesxe2x80x9d, J. Wiley 1985, page 490). Memory cells of this type are also referred to as EEPROM cells. They can be electrically programmed. However, time constants of up to 20 ms are required for writing data. These memories can be reprogrammed only to a limited extent, that is to say about 106 cycles. Furthermore, memory cells are known (see the reference by H. N. Lee et al, Ext. Abstr. Int. Conf. Solid State Devices and Materials, 1997, pages 382 to 383) in which memory cells each having a ferroelectric field-effect transistor are provided for the nonvolatile storage of data. Like a MOS transistor, the ferroelectric transistor has a source, a drain, a gate dielectric and a gate electrode, the gate dielectric containing a ferroelectric layer. The ferroelectric layer can assume two different polarization states, which are assigned to the logic values of a digital information item. By applying a sufficiently high voltage, the polarization state of the ferroelectric layer is altered. When the ferroelectric transistor is integrated in a silicon process technology, a dielectric intermediate layer is introduced between the surface of a silicon substrate and the ferroelectric layer, the intermediate layer ensuring the interface properties.
When the memory cell is programmed, part of the voltage applied between the silicon substrate and the gate electrode is dropped across the intermediate layer.
In order to avoid the technological difficulties of the interfaces, it has been proposed (see the reference by Y. Katoh et al., Symp. VLSI Technol., 1996, pages 56 to 57) to use, as a memory cell, a MOS transistor whose gate electrode is connected in series with a ferroelectric capacitor. In the memory cell, a voltage dependent on the polarization state of the ferroelectric layer of the ferroelectric capacitor is present at the gate electrode. In the memory cell, it is necessary that the connection between the gate electrode and the ferroelectric capacitor does not allow a charge flow, since otherwise the stored information is lost and the time for data retention does not suffice for nonvolatile storage.
It is accordingly an object of the invention to provide a memory cell configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is suitable for the nonvolatile storage of data and which can be reprogrammed more often than EEPROM configurations and in which the time for data retention is independent of leakage currents.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration. The memory cell configuration has a semiconductor substrate, and a multiplicity of memory cells each having a selection transistor with a terminal, a memory transistor with a control electrode, and a ferroelectric capacitor disposed in an integrated manner in the semiconductor substrate. The selection transistor and the memory transistor are connected in series through the terminal of the selection transistor. The ferroelectric capacitor is connected between the terminal of the selection transistor and the control electrode of the memory transistor.
The memory cell configuration has a multiplicity of memory cells each having a selection transistor, a memory transistor and a ferroelectric capacitor in an integrated manner in a semiconductor substrate. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a first terminal of the selection transistor, which is connected to a second terminal of the memory transistor, and a control electrode of the memory transistor.
The memory cell can be addressed in each case via a word line via which the selection transistor is switched on. If the selection transistor is switched on, then the potential present at the selection transistor is present directly at the memory transistor and at the ferroelectric capacitor. Depending on the polarization of the ferroelectric layer of the ferroelectric capacitor, the memory transistor is then switched on or not switched on. The level of the signal that is to be detected depends on the level that is present at the selection transistor. The memory cell is thus constructed in the manner of a gain memory cell.
The information is stored in the form of the polarization of the ferroelectric layer. The polarization can be switched over as often as desired. If a memory cell is selected by driving of the corresponding word line, then a fixed potential is present at the ferroelectric capacitor via the selection transistor. In accordance with the polarization of the ferroelectric layer, a voltage dependent on the stored information is present at the gate electrode of the storage capacitor. On the other hand, if the memory cell is not selected, then the potential can relax into equilibrium via possible leakage currents via the first terminal of the selection transistor. The information is not lost in the process. Only via the opening of the selection transistor is a defined potential once again applied to the ferroelectric capacitor and a voltage is once again present at the memory transistor.
Preferably, MOS transistors are in each case used for the selection transistor and the memory transistor. The control electrode of the memory transistor is then a gate electrode. The selection transistor is connected to a word line via its gate electrode. The selection transistor and the memory transistor are connected in series between a bit line and a reference line. The reference line and the bit line run parallel. The fact of whether one of these lines is used as a bit line or as a reference line is defined by the circuitry.
The ferroelectric capacitor has a ferroelectric layer disposed between two capacitor electrodes.
In order to write information to the memory cell, an increased voltage is applied between the bit line and the reference line, so that the polarization of the ferroelectric layer is altered. In this case, it is advantageous for the ratio of the capacitances of the ferroelectric capacitor and of the gate electrode of the memory transistor to be set essentially to 1:1. Since the dielectric constant of the ferroelectric layer (for example SBT=strontium bismuth tantalate) of the ferroelectric capacitor relative to the dielectric layer of the transistor (for example SiO2 in the standard silicon process technology) is approximately in a ratio of 100 to 1, in the event of an identical area of capacitor and transistor gate, a voltage divider with very unfavorable conditions is obtained. Preferably, however, the area proportions of the two components should be as small as possible and thus approximately identical. There are a number of possibilities for nevertheless improving the capacitance ratio of the voltage divider. The dielectric constant of the ferroelectric layer can be reduced by a suitable choice of the deposition conditions, for example a lower temperature budget, or by adding small quantities of niobium in the case of SBT. The capacitance of the ferroelectric capacitor decreases as a result.
On the other hand, it is possible in the region of the transistor to increase the gate capacitance by using, for example, CeO2, ZrO2 or a very thin nitrided silicon oxide as the gate dielectric for the transistor. The effect that can be achieved as a result is that the gate capacitance of the transistor considerably increases (for example by a factor of 5 for CeO2) in comparison with conventional SiO2 given a comparable layer thickness.
Furthermore, the capacitances can be suitably coordinated with one another by the layer thickness of the ferroelectric layer of the ferroelectric capacitor being, for example, a factor of 50 greater than that of the dielectric layer of the transistor.
In order to increase the capacitance between the gate electrode and the channel region of the memory transistor, it is advantageous to configure one of the source/drain regions of the memory transistor in such a way that it overlaps the gate electrode of the memory transistor. In this case, the overlap between the first source/drain region and the gate electrode of the memory transistor amounts to at least 10% of the area of the gate electrode.
Preferably, the memory transistor is connected to the reference line via a first terminal and a resistor is connected between the gate electrode of the memory transistor and the reference line. In the configuration, the read operation and the read/write memory write operation are separated in the time scale. In order to read the information, the memory cell is selected and a voltage is present at the gate electrode of the memory transistor for a time that depends on the resistor and the capacitance of the ferroelectric capacitor. The information can be read out during this time. After the time has elapsed the voltage is present directly at the ferroelectric capacitor, with the result that the polarization of the ferroelectric layer can be altered. Any resistor is suitable as the resistor in the configuration. It may have an ohmic characteristic curve. However, resistors without an ohmic characteristic curve are also suitable. In particular, the resistor can be realized by a thin dielectric layer through which charge carriers flow by tunneling. Such resistors are also referred to as tunnel resistor. In the configuration, the reference line is connected to zero volts and the bit line is connected to a supply voltage. The time constant is adjustable by way of the resistor and the capacitance.
A suitable semiconductor substrate is, in particular, a substrate that contains monocrystalline silicon, in particular a monocrystalline silicon wafer, an silicon on insulator (SOI) substrate or a SiC substrate.
Strontium bismuth tantalate (SBT), lead zirconium titanate (PZT), lithium niobate (LiNbO3) or barium strontium titanate (BST) can be used, inter alia, for the ferroelectric layer of the ferroelectric capacitor.
In accordance with another feature of the invention, the memory transistor has a terminal and a source/drain region connected to the terminal of the memory transistor and the source/drain region overlaps the control electrode of the memory transistor.
In accordance with a further feature of the invention, the overlapping between the source/drain region and the control electrode of the memory transistor amounts to at least 10% of an area of the control electrode.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.